//lt_ring.v
//logic test ring: Serial port, clk, reset_b, parallel port,
//bar LED, and test access through external SRAM pins
//external SRAMs disabled
//last updated 10/03/00
//Add your additional external ports in the following statement:
module mltring (clk, reset_b, RxD, TxD, rceb, lceb, dipsw);

//The following is the input from the internal/external clock
//on pin p89:

input clk;

//The following is the input for reset_b, which is the active low
//reset attached to sw<1>, the pushbutton on p174. If you want an
//active high reset, you need to invert reset_b.
 
input reset_b;

wire reset;
assign reset = ~reset_b;

//The following are the receive and transmit lines respectively
//for the serial port:

input RxD ;
output TxD ;

   
// The following are the chip enables for the left and right SRAMS:

output rceb ;
output lceb ;

parameter one = 1'b1;
assign rceb = one;
assign lceb = one;

//
// It is necessary to instantiate the clock buffer explicitly
// Note that the clock to be used in instantiating your top
// module is clk_buf instead of clk
//

wire clk_buf;
BUFGP clock_buf (.O(clk_buf), .I(clk));

//
// Add your additional external input/output declarations here!
//
wire [1:0] ioaddr;
wire iocs, iorw, tbr, rda;
wire [7:0] databus;
input [1:0] dipsw;
processor proc(.clk(clk_buf), .rst(reset), .databus(databus),
		.rda(rda), .tbr(tbr), .iocs(iocs),	.iorw(iorw),
		.ioaddr(ioaddr), .dipsw(dipsw));
spart spar(.clk(clk_buf), .rst(reset), .iocs(iocs), .iorw(iorw), 
		.ioaddr(ioaddr), .rda(rda), .tbr(tbr), .databus(databus),
	     .txd(TxD), .rxd(RxD));
   

  
//
//Instantiate the top module of your design here!
//
//Do not include any other code in this module or modify code 
//except as directed without instructor's permission!
//


   
endmodule 
